Suppress Echo of Command Invocation in Makefile

Suppress echo of command invocation in makefile?

Add @ to the beginning of command to tell gmake not to print the command being executed. Like this:

run:
     @java myprogram

As Oli suggested, this is a feature of Make and not of Bash.

On the other hand, Bash will never echo commands being executed unless you tell it to do so explicitly (i.e. with -x option).

How to suppress command output from makefile?

I have resolved that by redirecting error output into /dev/null:

nstop:
    @kill `cat ${APP_ROOT}/run/nginx.pid 2>/dev/null` 2>/dev/null ||:

But, I think, there should be better solution.

Meaning of @ sign in Makefile? (Not echo suppression nor automatic variable)

$@ is an automatic variable, see https://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html#Automatic-Variables

The file name of the target of the rule.

As far as the behavior caused by prepending $ to @, that's how variables work in make, see https://ftp.gnu.org/old-gnu/Manuals/make-3.79.1/html_chapter/make_6.html#SEC58

To substitute a variable's value, write a dollar sign followed by the name of the variable in parentheses or braces: either $(foo) or ${foo} is a valid reference to the variable foo. This special significance of $ is why you must write $$ to have the effect of a single dollar sign in a file name or command.

You can test this with an example:

SOMEVAR:=hello

test:
    echo ${SOMEVAR}
    echo $SOMEVAR
    echo $(SOMEVAR:hello=world)
    echo $($SOMEVAR:hello=world)

The behavior (echo output omitted) is:

echo hello
echo OMEVAR
echo world
echo

As you can see the last result is blank because make tries to resolve the OMEVAR variable, which is unset.

Suppress and ignore output for Makefile?

Actually, @- and -@ both do work, but will print a make: [target] Error 1 (ignored) warning.

Instead, you can use

@command || true

or, since : is shorthand for true in shell,

@command ||:

This often a better thing to do, because it avoid Make’s confusing warning that an error was ignored in an invisible command.

Consider the two most common cases where you might want to ignore the return value of a command:

1. Part of the build is broken and you want to continue anyway, in which case you’ve got some learning to do. The build is broken and needs to be fixed, not bandaided in an unmaintainable way.
2. A command returns a non-zero exit code even though it did exactly what you wanted, in which case you don’t really want Make to issue a warning.

For the second case, consider the example of grepping for warnings in the log file produced by a command. grep will return an error if it does not find a match, which is not what you want:

.PHONY: all one two three

all: at-warning at-success or-success or-warning

at-%: %.log
    @echo Making $@
    @-grep ^Warning $<

or-%: %.log
    @echo Making $@
    @grep ^Warning $< ||:

success.log:
    echo 'Success!' > $@

warning.log:
    echo 'Warning: foo' > $@

clean::
    rm -f {success,warning.log}

produces:

echo 'Warning: foo' > warning.log
Making at-warning
Warning: foo
Making at-success
make: [at-success] Error 1 (ignored)
Making or-success
Making or-warning
Warning: foo

Using @- produces a nonsensical ignored error warning when there is success, while || true handles both warnings and the absence of warnings without complaint.

Theoretically using || true is slower than using @-, but this overhead is unlikely to be a bottleneck in well-designed and -maintained build systems. The vast majority of the time should be spent building, or checking timestamps when there is nothing to build, not in running the thousands of quick commands whose return values all get ignored that would be necessary for this to have a measurable performance impact.

How to suppress echos in makefile?

you could add "@" before your command to surpress that echo

install: 
        @echo /usr/bin/shelldecrypt must be writable
        cp shelldecrypt /usr/bin

Control the output of a make command to be less verbose, don't echo each command

Well there's the usual business

target: dependency1 dependency2
    @echo Making $@
    @$(CC) -o $@ $(OPTIONS) $^

The leading @'s suppress the usual behavior of echoing the action without suppressing its output.

The output of various actions can be suppressed by redirecting it to /dev/null. Remember to grad the standard error too if you want a line to be really silent.

how to escape `& ` in Makefile?

The problem is not escaping. The problem is that is not legal syntax in the shell.

Make always invokes (by default) /bin/sh as the shell to run its recipes. /bin/sh is a POSIX-standard shell. The token &> is not valid POSIX shell syntax. When you are logged in at a shell prompt you are not running the shell /bin/sh, you are running a more powerful shell, probably bash (on Linux) or possibly zsh (on newer MacOS systems). These shells have extra features that are not defined in POSIX and not available in a POSIX-compliant version of /bin/sh.

You have two choices: either use correct POSIX syntax in your recipe:

run:
        python notation.py > notation.log 2>&1

Or else tell make to use your shell when it runs recipes:

SHELL := /bin/bash

run:
        python notation.py &> notation.log

(of course this assumes that all systems you want to run your makefile in, actually have /bin/bash installed)

Suppress messages in make clean (Makefile silent remove)

In fact I was looking for something else, adding this line to the Makefile :

.SILENT:clean

while execute every step of the "clean" target silently.

Until someone point some drawback to this, I use this as my favourite solution!

Getting Quiet Make to echo command lines on error

Tested and it worked (GNU make in Linux):

.c${MT}.doj:
     @echo "Compiling $<";\
          $(COMPILER) $(COPTS) -c -o $@ $<  \
          || echo "Error in command: $(COMPILER) $(COPTS) -c -o $@ $<" \
          && false

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