How to Clean Caches Used by the Linux Kernel

How to clean caches used by the Linux kernel

You may want to increase vfs_cache_pressure as well as set swappiness to 0.

Doing that will make the kernel reclaim cache faster, while giving processes equal or more favor when deciding what gets paged out.

You may only want to do this if processes you care about do very little disk I/O.

If a network I/O bound process has to swap in to serve requests, that's a problem and the real solution is to put it on a less competitive server.

With the default swappiness setting, the kernel is almost always going to favour keeping FS related cache in real memory.

As such, if you increase the cache pressure, be sure to equally adjust swappiness.

Flush CPU data caches in Linux kernel module

After some reflection I realised that the problem here is not really linked to data cache flushing. Actually I try to avoid a banal race condition (the first cpu clears value while the second increments it). In my case it's too expensive to protect data by mutex, so it's worth using atomic flag to notify the owning CPU to clear the values by itself.

How to purge disk I/O caches on Linux?

Sounds like you want the sync command, or the sync() function.

If you want disk cache flushing: echo 3 | sudo tee /proc/sys/vm/drop_caches

How to flush the CPU cache for a region of address space in Linux?

Check this page for list of available flushing methods in linux kernel: https://www.kernel.org/doc/Documentation/cachetlb.txt

Cache and TLB Flushing Under Linux. David S. Miller

There are set of range flushing functions

2) flush_cache_range(vma, start, end);
   change_range_of_page_tables(mm, start, end);
   flush_tlb_range(vma, start, end);

3) void flush_cache_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end)

Here we are flushing a specific range of (user) virtual
addresses from the cache.  After running, there will be no
entries in the cache for 'vma->vm_mm' for virtual addresses in
the range 'start' to 'end-1'.

You can also check implementation of the function - http://lxr.free-electrons.com/ident?a=sh;i=flush_cache_range

For example, in arm - http://lxr.free-electrons.com/source/arch/arm/mm/flush.c?a=sh&v=3.13#L67

 67 void flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
 68 {
 69         if (cache_is_vivt()) {
 70                 vivt_flush_cache_range(vma, start, end);
 71                 return;
 72         }
 73 
 74         if (cache_is_vipt_aliasing()) {
 75                 asm(    "mcr    p15, 0, %0, c7, c14, 0\n"
 76                 "       mcr     p15, 0, %0, c7, c10, 4"
 77                     :
 78                     : "r" (0)
 79                     : "cc");
 80         }
 81 
 82         if (vma->vm_flags & VM_EXEC)
 83                 __flush_icache_all();
 84 }

what is clean state in L2 cache?

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What is clean?

Clean, in ARM Cortex-A documents, usually means a flush (write dirty cache lines to next level). It is only valid for Dcache or unified caches. Some times we need both clean and invalidate (clear the cache). This is important if some other entity (bus master/peripheral) may change the memory. Usually, a bus (AXI) has a mechanism to avoid this. Also, if you update code in main memory and there is previous I-cache data, you need to invalidate it.

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Why multiple cleans?

You need to clean the L1 to make sure the data is in the L2 (flushed) so that you may then clean the L2. As we disable the L1 DCache, you may have some stale data from the act of L2 flushing in the L1. I am not completely sure why they say clean as opposed to invalidate for step 6. You haven't given an exact ARM CPU and these details vary depending on the type. It seems this is maybe an Cortex-A5/A8/A9 with external L2C-310.

The 2nd L1 clean is due to a race between the two levels of caches. It is describe in one of the Cortex-A technical reference manuals (TRM). I would follow their advice as it probably avoids some rare corner case and this type of code is difficult to debug. Shutdown/suspend/sleeping by necessity disables all your debug devices and is difficult to trouble shoot like boot code.

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