Run Executable from Makefile

Run Executable from makefile

If you run make without specifying any targets, it would execute the first target it finds within the Makefile. By convention all is the name of such a target.

If you make run a pre-requisite for all and mark both all and run as PHONY targets, you should be good to go.

all: run

run: prog1
    ./prog1

.PHONY: all run

BTW, I presume you already have some rules for building prog1 in your Makefile, and hence have not included it in the above shown Makefile.

An alternative would be to just invoke make explicitly with the run target, i.e. execute the following command:

make run

Running an executable with input using makefile

The executable doesn't take the input unless I type 100 7 4 again and press enter. How can I run it?

That executable probably expects data in its standard input rather than command line arguments:

run:
    echo "$(n1) $(n2) $(n3)" | ./block 

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I would normally have the following rule for running executables:

run_% : %
    echo "${$*.stdin}" | ./$< ${$*.args}
.PHONY: run_%

And then I would define an executable:

mytest : # something that builds mytest executable
mytest.stdin := "this goes into the standard input of mytest"
mytest.args := --verbose --dry-run

And invoke make like this:

make run_mytest

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Another point is that your recipes must produce the file they promise to produce. Presently, it promises to build a file named tiling, but builds one named block instead.

Fixes:

tiling:
    $(CC) $(tiling_file) -fopenmp -o $@

sequential: 
    $(CC) $(sequential_file) -fopenmp -o $@

In the above $@ stands for target name, tiling and sequential correspondingly.

How do I create a executable with a make file in c

 66 $(NAME):
 67     gcc -c $(FLAGS) -o ft_ls $(MAIN) $(OBJ)
 68     ar rc $(NAME) $(OB)

In the above snippet, you have a target $(NAME) [= ft_ls] without any dependencies and two commands, which are trying to create an executable and a library. Additionally you define a variable called OB but refer to a variable called OBJ. I suspect that you should only be creating an executable, like this

$(NAME): $(MAIN) $(OB)
    gcc $(FLAGS) -o ft_ls $(MAIN) $(OB)

If you are using GNU make then you can use $@ for the target and $^ for the dependencies (this makes your Makefile easier to maintain), like this

$(NAME): $(MAIN) $(OB)
    gcc $(FLAGS) -o $@ $^

It's not clear how your object files get compiled. If you just have a bunch of .c files and require some .o files then it's probably the suffix rule that gets used (see here), so you would need something like

.c.o:
        $(CC) -c $(FLAGS) -o $@ $<

makefile to run the code it compiles

You can't pass arguments to make like that. The command make run i.txt o.txt would attempt to build the rules run, i.txt, and o.txt.

What you could instead to is use a variable:

run:
    r.exe ${ARGS}

make run ARGS="i.txt o.txt"

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Side-note, rules should make the files that they say they do. So you really would want your compile rule to look like:

r.exe : main.cpp
    g++ -std=c++11 $^ -o $@

compile : r.exe
.PHONY  : compile

Is there a way to make a makefile for c++ that will run the program every time you use the make command?

You can simply add a new target to run the program and make that target depend on the creation of the program. If you make that target a dependency of the default target (all:) it will always run the program after a successful build.

Like this:

SOURCES = ./src/main.cpp

OBJECTS = ./bin/main.o

# default target to build hello executable & run it if successful
all: hello run

hello: $(OBJECTS)
    $(CXX) -o $@ $^

bin/%.o : src/%.cpp
    $(CXX) -c $(CPPFLAGS) $(CXXFLAGS) -o $@ $< $(LDFLAGS)

run: hello
    ./hello

clean:
    @rm -rf hello $(OBJECTS)

.PHONY: all run clean

Note: There is nothing special about the target name "run". I could have called it "wibble".

Run an executable after moving it to a different directory in the make file

You moved the program to ../Data/Derived/Release.

Then you tried to run ./Data/Derived/Release.

These are not the same path. .. means "the parent directory", but . means "this directory".

Looks like you missed out a dot.

Check executable is on a specific path in Makefile

You have to write your check recipe using shell syntax.

.PHONY: check-pip
check-pip:
         case "$(PIP)" in \
           ("$(DIRENV)"/*) echo "Found pip on the path" ;; \
           (*) echo "Cannot find pip"; exit 1 ;; \
         esac

Note, you need this if you only want to check this when the user specifically runs the check-pip target.

If you want to check it always whenever the user runs make regardless of which target they specify, then you can use makefile operations but you should not put them in a recipe, because they are run as the makefile is parsed not when a target is built. And you don't need a check-pip target at all.

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