Exclude Source File in Compilation Using Makefile

Is there a way to exclude certain source files or folders from a makefile?

That depends entirely how your makefile is written. You can use conditionals to avoid adding files given certain conditions hold:

 ifeq ($(OS),win32)
 SOURCES += foo_win32.cpp
 else
 SOURCES += foo_posix.cpp
 endif
 ...
 foo: $(SOURCES)

If you elaborated a little on exactly you want to do, you may get a better answer.

EDIT: If the files are determined by running find, you can exclude files/directories from find like this:

SOURCES:=$(shell find srcdir -type f | grep -v dirtoexclude)

Makefile. How to exclude one particular file from compilation?

That isn't the best way to do it, but if you do it along these lines, write it as a shell condition, not using GNU make conditionals:

$(TMPDIRPATH)%.o: %.cpp
    @echo compile $<
    @if [ $(notdir $<) != main.cpp ]; \
    then $(COMPILE.cpp) $(OUTPUT_OPTION) $<; \
    fi

The continuation markers (backslashes) are needed. So are the semicolons. The values prefixed with $ will be expanded by make before the shell is invoked to interpret them. You probably don't want the echo where it is, either. You probably need:

$(TMPDIRPATH)%.o: %.cpp
    @if [ $(notdir $<) != main.cpp ]; \
    then echo compile $<; \
         $(COMPILE.cpp) $(OUTPUT_OPTION) $<; \
    fi

The way I would expect to do it is with a list of the files to be compiled. Using any wild card mechanism leads to problems when extra files are added - other tests, or stray files that aren't really part of the system.

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The comment says "But the GNU Make Manual says ifneq should work".

The ifneq would work if it were positioned correctly, which means 'not indented as part of the commands associated with a rule'. You could, therefore, write something like (an appallingly bad example, but my brain's on the fritz):

ifneq (${CFLAGS}, -Wall)
CFLAGS += -Wall
endif

file1.o: file1.c
    ${CC} ${CFLAGS} -c $<

But when the ifneq is indented as in the question, it is just a command that actually isn't found on the system when the make runs the shell to process the command.

Makefile excluding files

If the elements in NEWSRC necessarily start with
../sources/filesystem/SomePath, how about adding suffix to EXCLUDES as
the following?

$(filter-out $(addsuffix /%,$(EXCLUDES)),$(NEWSRC))

How can I exclude a file from g++ compiler options

The make utility provides a rich set of facilities for customizing builds and for defaulting to implicit procedures for things that are routine logic. The GNU make tutorial is a good starting point if there's a question related to the gcc toolchain.

Essentially a makefile contains the custom logic for building a project. Rules consist of an apparent target separated from the dependencies by a colon on one line, and then (possibly zero or many) recipes on succeeding lines indented by a tab character that explain steps in building that target. Bogus targets, eg. clean, may also be defined for convenience in maintaining a project.

If there's a target-specific rule, that will be used in preference to any implicit rule to build that target. Probably the OP only needs to add a target-specific rule to an existing makefile that will govern the use of compiler options (building the object from the source).

exclude file from rm in makefile

If you're using GNU make you could do it like this:

clean_target:
        rm -rf *.mcs *.bit *.bin *.twr *.pwr *.tsi *.twx *.ncd *.pcf *.ngd \
            $(filter-out FIFO.ngc,$(wildcard *.ngc))

Makefile how to not remove one specific object file while remove all other object files and executable files?

Firstly, do not issue wildcard remove commands in a clean: rule (or any other). When the user types make clean, they could lose files that is not even under the control of the build system. Your build system should only clean what it builds. (That is, at least with the "regular strength" clean target; here we should acknowledge the widespread practice of providing additional targets that remove editor backup files, tags, generated configuration materials and whatnot.)

The object files should be listed in some variable like $(OBJS) and should be removed using rm -f ... $(OBJS).

If a certain object file is not to be removed, you can divide things:

DISPOSABLE_OBJS = ...
PRECIOUS_OBJS = ...
OBJS = $(DISPOSABLE_OBJS) $(PRECIOUS_OBJS)

Then in the clean rule, just remove the $(DISPOSABLE_OBJS).

In GNU Make you have additional flexibilities, like rm -f $(filter-out keep1.o keep2.o,$(OBJS)) to remove all $(OBJS) except keep1.o and keep2.o.

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