ModelSim-Altera error
Eureka! I've googled the following text: error while loading shared libraries: libXft.so.2: cannot open shared object file: No such file or directory Error.
I've found out (thanks to Qiu as well) that I need to install 32bit packages for my 64bit OS that the ModelSim-Altera software uses. Here are is the proper command to enter to the Ubuntu terminal:
sudo apt-get install libxft2 libxft2:i386 lib32ncurses5
And problem solved!
ModelSim-Altera show error enum literal name already exists while Quartus not
IEEE 1800-2012, section 6.19 says:
// Correct declaration - bronze and gold are unsized
enum bit [3:0] {bronze='h3, silver, gold='h5} medal2;
// Correct declaration - bronze and gold sizes are redundant
enum bit [3:0] {bronze=4'h3, silver, gold=4'h5} medal3;
Type checking of enumerated types used in assignments, as
arguments, and with operators is covered in
6.19.3. As in C, there is no overloading of literals; therefore, medal2 and medal3 cannot be defined in the same scope because they
contain the same names
So, I would say that it is correct to report an error with your code because the IDLE
literal appears twice.
I have tried your code on three simulators. One accepts it, the other two reject it. So, in total, three simulators reject your code, one accepts it (as does Quartus). I guess the fact that your enum is declared within a struct complicates the EDA vendors' interpretation of the standard.
The fix is to change the name of one or both (eg IDLE1
and IDLE2
).
ModelSim Altera 10.1d - verilog I can't get wave forms
forever ck=~ck;
is a zero time infinite loop. The simulation will not move to the next time step until all operations on the current time step is completed (which is impossible when there is a zero time infinite loop).
Adding time delay to your clock will help. For example: forever #5 ck=~ck;
Check your log file. Some simulators will report errors or warnings when they encounter an infinite loop.
ModelSim: Intel On-Chip Flash IP: Error: (vsim-3033) Instantiation of 'altera_onchip_flash_block' failed
As you already realized, this is a precompiled IP-Core. Normally these precompiled IP-Cores come with files for simulation.
This pdf includes a step-by-step tutorial to instantiate the IP-Core and generate simulation files with Quartus (on page 12 of 36 or section 4-2).
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