C++ Makefile on Linux with Multiple *.Cpp Files

C++ makefile on Linux with Multiple *.cpp files

you'll need to compile all .cpp files that you use (i assume they are not included somewhere).
That way the compiler will know that file1.cpp and main.cpp are used together.
Also I would suggest using g++ instead of gcc, because g++ is the specific c++ compiler while gcc supports C and C++.

Try using:

g++ -g -Wall -o main main.cpp file1.cpp

Also I would recommend to use Makefile variables like this:

SOURCES = main.cpp file1.cpp
g++ -g -Wall -o main $(SOURCES)

Hope this helps :)

Using G++ to compile multiple .cpp and .h files

list all the other cpp files after main.cpp.

ie

g++ main.cpp other.cpp etc.cpp

and so on.

Or you can compile them all individually. You then link all the resulting ".o" files together.

Makefile export .o file to a different path than .cpp

Use make -d or even better remake -x to understand what commands are invoked.

Run also make -p to understand what builtin rules are used.

We cannot help you more, because we have no idea if you redefined CFLAGS.

And C++ compilation should better be done with g++ that is CXX and CXXFLAGS, e.g. with (I am extracting this from my make -p output)

LINK.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(LDFLAGS) $(TARGET_ARCH)
COMPILE.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(TARGET_ARCH) -c
CXX = g++
%.o: %.cc
      $(COMPILE.cc) $(OUTPUT_OPTION) $<

I strongly suggest to have CXXFLAGS= -Wall -g at least during the development phase. Learn also to use gdb and valgrind.

You could have the following in your Makefile

 CXXFLAGS= -g -Wall
 SOURCES=f1.cc f2.cc
 SOURCE_PATH=yoursourcedir/
 OBJECT_PATH=yourobjectdir/
 SRCFILES=$(patsubst %.cc,$(SOURCE_PATH)/%.cc,$(SOURCES))
 OBJFILES=$(patsubst %.cc,$(OBJECT_PATH)/%.o,$(SOURCES))
 PROGFILE=$(OBJECT_PATH)
 .PHONY: all clean
 all: $(PROGFILE)
 $(PROGFILE): $(OBJFILES)
         $(LINK.cc) $^ $(LOADLIBES) $(LDLIBS) -o $@
 $(OBJECT_PATH)/%.o: $(SOURCE_PATH)/%.cc
         $(COMPILE.cc)  $(OUTPUT_OPTION) $<
 clean:
         $(RM) $(OBJECT_PATH)/*.o $(PROGFILE)

Building using Makefile: picks file.c instead of file.cpp even though specified explicitly

The method make uses to pick which of two possible matching rules gets used depends on which version of make you are using. (It changed between 3.81 and 3.82 and I believe got tweaked slightly for 4.0+ but am not certain about that.)

I believe make 3.81 used the last matching rule and make 3.82+ uses the matching rule with the shortest stem (the bit that matches the %) and then the first matching rule between rules that have similar stem lengths.

So it would seem like you are using make 3.81 currently.

In that case it should be possible to simply swap the order of your two rules to get the behavior you want (assuming you always want .cpp files to "win").

Alternatively you could try giving make an explicit prerequisite for the file3.o target instead of letting it guess. (i.e. file3.o: file3.cpp)

That said neither of your explicit suffix rules is necessary as make already contains default rules to build .o files from both .c and .cpp files. (I don't know the relative ordering between them so you likely will need the explicit prerequisite, assuming that works, for the built-in rules to work correctly.)

Also you might want to look at using Pattern Rules instead of Old-Fashioned Suffix Rules just as a point of current practice.

The only improvement to your populating the OBJS variable that I can see, offhand, is to filter on the results and so just filter once.

OBJS = $(filter %.o,$(patsubst %.cpp,%.o,$(SOURCE_FILES)) \
    $(patsubst %.c,%.o,$(SOURCE_FILES)))

That said you could also use Substitution References instead of explicit calls to $(patsubst) to shorten that a bit.

OBJS = $(filter %.o,$(SOURCE_FILES:.cpp=.o) $(SOURCE_FILES:.c=.o))

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